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CHIP-ARCHITECT  PUBLICATIONS

  Mar 23, 2003 Prescott / Nocona doubles number of in-flight instructions
  Mar  6,  2003 Looking at Intel's Prescott die

Jun  24,  2002

The Two Extra Pipeline Stages of the AMD Hammer
 Apr  16,  2002 Intel's Prescott Prospects  .
 Dec  11,  2001 Size and Speed of the 130 nm Northwood Pentium 4
 Oct  18,  2001 AMD goes for the performance crown
 Oct    7,  2001 AMD: Long Term Options
 Oct    2,  2001 AMD's 8th generation Hammer processor: A Micro Architecture preview
 Nov  25, 2000 Motorola/AMD's HiP7: A dream process but still a year away
 Nov    7, 2000 Intel's and Motorola/AMD's 130 nm processes to be revealed
 Nov   7,  2000 Speculative Intel adder adds twice as fast 95% of the time
 Oct  13,  2000 An analysis of the newly presented Pentium 4 core.
 Oct  10,  2000 Willamette news and surprises from the Microprocessor Forum.
 Sep  27,  2000 Patents with a new AMD Micro Architecture.
 Aug  25,  2000 Intels Developers Forum
 Jun   29,  2000 Mustang to reach 1.3 GHz debut speeds already at 180 nm
 Jun   23,  2000 News on Willamette's Cache organisation
 Jun     2,  2000 Ashok Kumar mentions 170 mm2 for Willamette's Die size
 Jun     1,  2000 Correction on the Branch Prediction hardware
 May   5,  2000 AMD's Mustang versus Intel's Willamette (PDF)

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address generator
ALU
branch miss prediction penalty
branch prediction
cache
cache hit
cache miss
data cache
dynamic predictor
instruction cache
instruction decoder
instruction pipeline
instruction pre-fetch
instruction sheduler
renamed register file
macro-op
micro-op
predictor selector
processor
processor pipeline

hyper pipelining

hyper threading

simultaneous multi threading
static predictor
trace cache

3dnow
SSE
SSE2
MMX
XMM

Athlon
Thunderbird
Spitfire
Duron
Mustang
Corvette

Palomino

Apalona

Thoroughbred

Barton

Sledgehammer
Clawgehammer
Opteron

Pentium 4
Willamette
Foster
Gallatin

Prescott

Nocona
Northwood

Hans de Vries
Hans Devries