Kalla together with Balaram Sinharoy and Joel Tender introduced IBM's next generation POWER
5 microprocessor. The Power 5 is an improved dual
core Power 4 micro architecture extended to support two
virtual processors per core. The core sizes are increased
with 24% Performance improvements of 40% are seen for
multi threaded applications.
recourses are extended or improved which also improves the
single thread performance. It was estimated that the
multithreading performance improvement would have been limited
to 20% without these extensions. More information will be made
available during this years Micro Processor Forum in October.
/ Improved Resources:
General Purpose Renamed Register File (80 ->
Floating Point Renamed Register File (80 ->
Instruction Fetch Buffers
Address Translation Tables:
- SLB (Segment Look aside Buffer
- TLB (Translation Look aside Buffer)
- ERAT (Effective to Real Address Table)
Instruction and Data Caches ( higher associativity )
shared by the threads:
Global Completion Table (Retirement),
Branch History Table (BHT),
Address Translation Look aside Buffer (TLB)
Thread can be either Active or Dormant. A dormant thread wakes
up on an external interrupt, a decrementer interrupt (timer) or
a special instruction from the active thread.
relative activity of the two threads can be managed by
software/hardware by controlling the Instruction decode rate for
the two threads. There are 8 priority levels for each thread.