Here we show a few fragments from a paper from Tong Liu and Shih-Lien Lu of Intel that will be presented at the 33rd International Symposium on Microarchitecture in Monterey on December 13, 2000
It describes a speculative adder that has a latency which is 1/2 that of a normal adder. It predicts the
right answer in 95% of the cases. The big question now: Is an adder like this used in the Rapid Execution Engine of the Pentium 4? Intel maintains that it can add twice as fast as held possible.. 

Well.. For the moment we keep believing that the adder in the Rapid Execution Unit uses CSA tricks to achieve the effective 1/2 cycle latency. This because non of the examples given by Intel on various occasions contradicts the use of a CSA. The adder below would introduce extra complications because of the abort/ replay mechanism needed in case of a miss-prediction. We'll know more in February when Intel will describe the Rapid Execution Unit in more detail during the ISSCC'2001